1. Field of the Invention
The present invention relates to techniques for assembling systems containing semiconductor dies. More specifically, the present invention relates to a method and an apparatus that facilitate fluidic self-assembly of semiconductor dies in multi-chip modules.
2. Related Art
Advances is semiconductor technology presently make it possible to integrate large-scale systems, which can include hundreds of millions of transistors, into a single semiconductor chip (or die). Integrating such large-scale systems onto a single semiconductor chip increases the speed at which such systems can operate, because signals between system components do not have to cross chip boundaries, and are not subject to lengthy chip-to-chip propagation delays. Moreover, integrating large-scale systems onto a single semiconductor chip significantly reduces production costs, because fewer semiconductor chips are required to perform a given computational task.
Unfortunately, these advances in semiconductor technology have not been matched by corresponding advances in inter-chip communication technology. Semiconductor chips are typically integrated onto a printed circuit board that contains multiple layers of signal lines for inter-chip communication. However, signal lines on a semiconductor chip are about 100 times more densely packed than signal lines on a printed circuit board. Consequently, only a tiny fraction of the signal lines on a semiconductor chip can be routed across the printed circuit board to other chips. This problem has created a bottleneck that continues to grow as semiconductor integration densities continue to increase.
Researchers have begun to investigate alternative techniques for communicating between semiconductor chips. One promising technique involves integrating arrays of capacitive transmitters and receivers onto semiconductor chips to facilitate inter-chip communication. If a first chip is situated face-to-face with a second chip so that transmitter pads on the first chip are capacitively coupled with receiver pads on the second chip, the first chip can directly transmit signals to the second chip without having to route the signals through intervening signal lines within a printed circuit board.
Capacitive coupling requires precise alignment between the transmitter pads and the receiver pads (which are more generally referred to as proximity connectors), both in a plane defined by the pads and in a direction perpendicular to the plane. Misalignment between the transmitter pads and the receiver pads may cause each receiving pad to span two transmitting pads, thereby destroying a received signal. In theory, for communication to be possible, chips must be aligned so that misalignment is less than half of a pitch between the pads. In practice, the alignment requirements may be more stringent. In addition, reducing misalignment can improve communication performance between the chips and reduce power consumption.
Unfortunately, it can be very challenging to align chips properly. Existing approaches include mechanical mounting structures that facilitate self-alignment and/or self-adjustment of pad positions. FIG. 1 illustrates one such approach in which negative features, such as etch pits 112, and micro-spheres 114 are used to align semiconductor dies 110 (and thus proximity connectors) in a multi-chip module (MCM). These etch-pits can be defined photolithographically using a subtractive process (i.e., a photolithographic process that removes material), which takes place before, during, or after circuit fabrication on the semiconductor dies 110. This enables the etch pits 112 to be accurately placed on the semiconductor dies 110 in relationship to circuits and the proximity connectors. Therefore, the photolithographic alignment between the etch pits 112 and circuits establishes precise alignment between circuits on the top and bottom semiconductor dies 110.
Note that the alignment in the X, Y, and Z directions, as well as the angular alignment between semiconductor dies 110, depends only on the relative sizes of the etch-pits 112 and the micro-spheres 114, and on the orientation and placement of the etch pits 112 on the semiconductor dies 110. In particular, the lateral alignment between circuits on the semiconductor dies 110 is achieved in a ‘snap-fit’ manner, provided the micro-spheres 114 are appropriately sized to fit into the etched pits 112. Clearly, micro-spheres 114 that are too large do not fit into the etch pits 112, and micro-spheres 114 that are too small do not properly align the top and bottom semiconductor dies 110. However, if the micro-spheres 114 sit in the groove of the etch pits 112 correctly (for example, their equators lie exactly at or higher than the surface of the semiconductor die 110-1 and exactly at or lower than the surface of semiconductor die 110-2) then circuits on the top and bottom semiconductor dies 110 are precisely aligned. Similarly, alignment in the Z direction is a function of the photolithographic feature size of the etch pits 112, the etch depth of the etch pits 112, and the diameter of the micro-spheres 114.
While this approach is useful and applicable to packaging and assembly of MCMs that include two or more semiconductor dies 110, it suffers from the limitation that the placement of micro-spheres 114 into the etch-pits 112 is not a parallel, wafer-scale process that can be readily performed at a foundry. Instead, the micro-spheres 114 are often placed into individual semiconductor dies 110 after fabrication. Consequently, this approach may add complexity and cost to the process of assembling MCMs.
Hence, what is needed is a method and an apparatus that facilitates aligning proximity connectors without the problems listed above.